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Job Description

Join Intel and build a better tomorrow. Intel is in the midst of an exciting transformation, with a vision to create and extend computing technology to connect and enrich the lives of every person on Earth. So join us and help us create the next generation of technologies that will shape the future for decades to come.

To support Intel IDM2.0 Foundry strategy, we are looking for talents to join this exciting journey to drive design enablement with focus on quality and reliability area to build industry competitive design platform supporting both internal design and external designs on Intel leading edge technologies. The general reliability design enablement includes pathfinding and development in PDK (Process Design Kits), TFM (tool/flow/methodology, IP (library, memory, analog IP) and DFR (Design for Reliability) to achieve best PPA (Power Performance Area) and reliability co-optimization.

As a technical lead, you will be responsible for but not limited to one or more of the following areas:

• Pathfinding and development of design and reliability TFM (tool/flow/methodology), drive industry EDA (Electronic Design Automation) tool enablement and solution, covering electrical, thermal, power, reliability assessment and multi-physics analyses from transistors to interconnect, IP, SOC and 3DIC integration.

• Exploration and enablement of novel tool, flow and capability including AI/ML in design for reliability/manufacturing/yield to drive EoU and design efficiency to achieve optional PPA and reliability and enable internal and external design on Intel leading edge technology node for different market segment from commercial to automotive and AI application.

• Development and program management of PDK with focus on reliability components including design rule, tech-file, design collateral to enable internal and external design on Intel leading edge technology nodes, spanning from transistor, interconnect to package and 3DIC integration.

• Competitive benchmarking, DTCO/STCO (Design/System Technology Co-Optimization) for technology definition and design enablement in reliability domain, enable and deliver industry leading PDK, design rule, TFM and IP ecosystem for ease of design and fast to market.

The Candidate Should Exhibit the Following Behavioral Traits:

• Written and verbal communication and presentation skills.

• Demonstrated experience working with and or managing teams using and converting technical data into presentations.

• Passion for quality and attention for details and procedures.

• Demonstrated capability to drive quality enhancements projects.

• Team player with proven ability to work in diverse multi-cultural environment.

• Ability to work effectively within a global team spanning multiple countries and cultures.

• Leadership capabilities building, motivating, coaching, and directing cross-functional teams and team members to meet project objectives.

• Must be flexible and adaptable to ensure program commitments are met on time in a dynamic work environment.

#DesignEnablement

Qualifications

You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the requirements and are considered a plus factor in identifying top candidates.

Minimum Qualifications:

Candidate must possess a BS degree with 4+ years of experience or MS degree with 3+ years of experience or PhD degree with 1+ years of experience in electrical engineering, physics or a related field.

Experience in one of the following areas:

PDK development or program management , reliability tool and flow development, design for reliability, IP and SOC design reliability validation using PDK and/or EDA tool and flow.

Preferred Qualifications:

Experience in the following:

• Experience on EDA tool/flow development and modeling Multiphysics interactions between performance, power, thermal, reliability validation for advanced Si and package technology.

• Knowledge on design flows, design rules, physical layout and simulation-based validation and implementation in EDA tools for reliability, timing and thermal analysis at multiple time and spatial scales.

• Experience to work with Foundry, fabless company, EDA vendor and IP design house for co-optimization.

• Understanding of industry standard practice and methodology in PDK, TFM and IP design verification.

• Experience on PDK development; knowledge and understanding of PDK fundamentals; reliability design rules and their implementation in PDK and TFM for commercial and automotive requirements.

• Experience and knowledge on reliability verification and physics, such as aging including BTI (Bias Temperature Instability) and HCI (Hot Carrier Injection), Electro-Migration, high voltage design, EOS (Electrical Over-Stress), ESD (Electrostatic Discharge).

• Experience on design flow and practices and their application in IP and SOC design validation and sign-off; able to conduct design impact and risk assessment in related reliability areas.

• Experiences and skills in program management, stakeholder management, and strong communication skills.

Inside this Business Group

As the world's largest chip manufacturer, Intel strives to make every facet of semiconductor manufacturing state-of-the-art -- from semiconductor process development and manufacturing, through yield improvement to packaging, final test and optimization, and world class Supply Chain and facilities support. Employees in the Technology Development and Manufacturing Group are part of a worldwide network of design, development, manufacturing, and assembly/test facilities, all focused on utilizing the power of Moore’s Law to bring smart, connected devices to every person on Earth.

Other Locations

US, TX, Austin; US, AZ, Phoenix; US, CA, Folsom; US, CA, Santa Clara

Posting Statement

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Benefits

We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing Benefits here. (https://jobs.intel.com/en/benefits)

Annual Salary Range for jobs which could be performed in US, California: $144,501.00-$217,311.00

*Salary range dependent on a number of factors including location and experience

Working Model

This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. In certain circumstances the work model may change to accommodate business needs.