Qualcomm SoC Infrastructure deployment Engineer - Qualcomm - Guyancourt, France in France
Company:Qualcomm France S.A.R.L.
Job Area:Engineering Group, Engineering Group > ASICS Engineering
Qualcomm is a company of inventors that unlocked 5G ushering in an age of rapid acceleration in connectivity and new possibilities that will transform industries, create jobs, and enrich lives. But this is just the beginning. It takes inventive minds with diverse skills, backgrounds, and cultures to transform 5Gs potential into world-changing technologies and products. This is the Invention Age - and this is where you come in.
Qualcomm Interconnect Technology (QITC) has been breaking ground in interconnect design for 15 years and continues to innovate and deliver technology in line with the very latest evolutions in SoC design.The QITC mission is to develop and deploy custom-built interconnect hardware IPs, software tools, and exploration and verification methodologies so that SoC integration teams can quickly assemble SoCs with the desired Power Performance Area (PPA) characteristics.To this end, QITC technology embraces the complete SoC infrastructure to provide increased SoC performance at minimal cost for integration. Our work is at the backbone of the SoC, interconnecting all major IP solutions.You will be in charge of deploying this technology across all kind of SoC (Mobile, Automotive, Servers, IoT, Connectivity, ).You will work in a multinational environment and with cross-functional teams (Architecture, HW and SW Design, Verification, Debug, Post Silicon).Minimum QualificationsBachelor's degree in Science, Engineering, or related field.Preferred QualificationsIdeally you have a good understanding of overall SoC development flow : SoC architecture, SystemC modeling, RTL design and verification, SoC performance and DDR memory channel, physical implementation, silicon debug. In addition you have knowledge of arm based protocols. Knowledge of Multimedia Ips and/or Modem is a plus.Interconnect technology includes:Configurable memory map and security schemeCache coherent infrastructureVarious protocol support (AMBA, custom interface for high performance multimedia IP, interNoC socket, configuration, )Silicon debug units for efficient SoC bringupQuality of Service, buffering, splitting, shaping, and dynamic priority for complex SoCHigh degree of configurability for Power Performance Area tradeoffs.
*References to a particular number of years experience are for indicative purposes only. Applications from candidates with equivalent experience will be considered, provided that the candidate can demonstrate an ability to fulfill the principal duties of the role and possesses the required competencies.
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